1. Field of Invention
The present invention relates to a structure for manufacturing a semiconductor device. More particularly, the present invention relates to a structure for reducing stress between a metallic layer and a spin-on-glass layer.
2. Description of Related Art
As the level of integration for semiconductor devices increase, there will be insufficient room on the surface to provide the necessary interconnects. To match the increase in interconnects necessary for connecting the increase number of metal oxide semiconductor (MOS) transistors after miniaturization, designs having two or more metallic interconnect layers are quite common.
Between two metallic layers, there must be an inter-metal dielectric layer for isolating and blocking the formation of unnecessary electrical circuits. Therefore, properties of the inter-metal dielectric layer are very important. In another aspect, the inter-metal dielectric layer is important because the ease and quality of subsequently deposited metallic layer, subsequent etching processes and resolution in a photolithographic process all depend on the degree of planarization of this layer.
Conventional method of isolating two metal layers includes using material such as tetra-ethyl-ortho-silicate (TEOS). However, the TEOS involves reaction at a rather high temperature of about 650.degree. C. to 750.degree. C. In addition, the degree of planarization of the deposited material is poor, and so a planarization operation such as a chemical-mechanical polishing (CMP) must be performed. Hence, in recent years, hydrogen silsesquioxane (HSQ) is gradually replacing TEOS as the material for forming inter-metal dielectric layers.
HSQ is a type of spin-on-glass (SOG) material that is extensively used the fabrication of semiconductor structures. HSQ is a suitable material for forming inter-metal dielectric layers because of its special properties. Properties of HSQ include a low dielectric constant, free from carbon and reflowable. Consequently, there is no need to perform etchback operations, which have a high risk of contamination, when using HSQ. Furthermore, since the HSQ has a good gap filling capability, processing steps can be reduced and production cost can be saved. In another aspect, the Si--H bonds formed inside a HSQ layer can prevent the absorption of moisture. Therefore, using the HSQ to perform direct-on-metal and non-etchback operation is capable not only of good planarization, but also able to obtain a low parasitic capacitance. Moreover, no chemical-mechanical polishing operations are necessary, and so some cost is saved.
FIGS. 1A and 1B are cross-sectional views showing the progression of steps in a conventional planarization process using HSQ in a direct-on-metal and non-etchback approach. In FIG. 1A, MOS devices and silicon substrate 10 below a metallic layer 12 are not drawn. First, as shown in FIG. 1A a dielectric material such as HSQ is mixed and then dissolved in a solvent to form a liquid state dielectric source solution. Thereafter, the dielectric solution is spin-coated onto the silicon substrate 10 to form an inter-metal dielectric layer 16. Due to the reflowability of HSQ, the spin-coated HSQ layer has a good gap filling capability.
Next, as shown in FIG. 1B, since the spin-coated HSQ dielectric layer 16 has solvent in it and the surface of the HSQ dielectric layer 16 is rather uneven, hence, heat flowing and curing operations need to be performed. First, as a preliminary step, a hot baking process is performed using, for example, a hot plate, at a temperature of about 150.degree. C. for about 8 to 12 minutes. In the process, most of the solvent in the HSQ dielectric layer 16 is driven out and Si--O bond forming is initiated.
Thereafter, the temperature is raised to about 200.degree. C. for a period of about 18 to 22 minutes for melting the dielectric layer 16. Subsequently, the temperature is raised to about 350.degree. C. for another 18 to 22 minutes to start the heat flow operation. Hence, the degree of planarity of the HSQ dielectric layer 16 is increased and the effect of an undulating metallic layer 12 on the HSQ dielectric layer 16 is minimized. Finally, the temperature is raised to about 400.degree. C. for about 18 to 22 minutes. At a high temperature, the residual solvent is driven away accompanied by the densification of the HSQ dielectric layer 16, and finally the layer is cured into a SiO.sub.2 -like structure.
However, due to the considerable volume contraction during the hot baking, heat flow and curing processes, high tensile stress will build up between the deposited spin-on-glass HSQ layer 16 and the underlying metallic layers 12. Furthermore, spin-on-glass structure has a weaker bonding strength compared with an oxide layer formed by a chemical vapor deposition method and a smaller coefficient of expansion compared with metal. Therefore, cracks are easily formed in the dielectric layer 16 due to subsequent thermal cycling.
In light of the foregoing, there is a need to provide a better method for forming the HSQ dielectric layer in order to reduce the internal tensile stress.